The BOT40 Controller pcb is shown here. Starting in the center and going clockwise, chips are PIC controller (U1), L293D H-bridge chips (U3, U4), RS-232 interface (U5), and I²C serial EEPROM (U2).

Top: 7805-type voltage regulator circuit. Resistor nets RN2-RN4 form an R-2R ladder network for sensing 4 external switches (eg, bumpers) via header HDR2. This produces perfectly linear voltages at A/D chan RA3. Below this is ICSP header. On right is layout for a piezo element.

Middle: Prototyping area on the left is laidout to facilitate mounting additional chips, as well as custom circuitry for cpu pins RA0-2, RA4, RA5, RC0, RC5, and RE0-RE2. Jumpers J2-J5 configure EEPROM control by RA4/RA5 (for OOPic), or by RC3/RC4 (PIC Sclk/Sdat).

The highly-versatile Q1-Q3 area to the right can be configured for bipolar and/or MOSFET transistor drivers - p-type or n-type, inverter or non-inverter - up to 5A. HDR5 directly interfaces up to 8 Futaba-pinout servos (signal-power-gnd) - limited to 5, when Q1-Q3 are used.

Bottom: RS-232 port on left. Chan 1 interfaces the cpu UART to both P1 (DB09-F) and HDR6. Chan 2 is non-dedicated, and connects to HDR7 (hi-side) and Rc2/Tc2 (lo-side). At right, the (2) L293D chips provide 8 push-pull driver channels (4 full h-bridges) for motor control. The motor buss is heavily filtered by C13, C14, and transzorb TZ1. Switch SW1 and (4) LEDs are available for general use.

Ground Busses: The outermost row of pins on every board-edge header is all grounds - which greatly facilitates making convenient 2-wire connections. The motor ground busses on the right are electrically isolated from the cpu logic buss and connected at 1-point via Z1, inductor or ferrite (next to the piezo).

Physical: 3.0" x 4.0" (76 x 102 mm), top and bottom solder masks, and silk-screened.

SBC40-BOT Headers